The semiconductor industry has continually improved the processing capabilities and power consumption of integrated chips by shrinking the minimum feature size of chip components (e.g., by shrinking the minimize gate size of a transistor through improvements in lithographic processes). However, in recent years process limitations have made it difficult to support the continued shrinking of minimum feature size.
The vertical stacking of integrated chips (e.g., on top of one another) has emerged as a potential alternative approach to improving integrated chip performance by shrinking the minimum feature size. For example, a three dimensional integrated chip (3DIC) is a single integrated circuit built by vertically stacking silicon die. By interconnecting the vertically stacked silicon die to behave a single chip, the interconnection distance is shortened, improving processing capabilities and reducing power consumption.
In many stacked chip structures, an interposer substrate (e.g., glass or silicon interposer substrates) is configured between stacked integrated chip (IC) die to provide for structural stability, improved heat dissipation, improved interconnection, etc. The wiring on a stacked IC die corresponds to a location of micro-bumps on the interposer substrate. The micro-bumps connect respective IC dies to through silicon vias (TSV), which are vertical electrical connections extending through the interposer substrate (e.g., to provide connections from an upper die to a lower die).
During processing, an IC die is aligned with a micro-bump region and then the IC die is brought into contact with an interposer substrate. The IC die and interposer substrate are heated, causing the micro-bumps of the IC die to fuse with the corresponding micro-bumps of the interposer substrate. In general, alignment of an IC die to a micro-bump region is done by manual alignment. Since micro-bump regions are small, alignment is difficult and can be time consuming.